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Mechanical Dimensions
5.00
8
4.80
3.81
5
A
B
0.65
6.20
5.80
PIN ONE
1
4
4.00
3.80
1.75
5.60
INDICATOR
(0.33)
1.27
0.25
M
C B A
1.27
LAND PATTERN RECOMMENDATION
0.25
SEE DETAIL A
0.10
0.25
1.75 MAX
0.51
0.33
C
0.10 C
OPTION A - BEVEL EDGE
0.19
R0.10
0.50 x 45
0.25
GAGE PLANE
R0.10
8
0
0.90
0.406
0.36
SEATI NG PLANE
(1.04)
DETAIL A
SCALE: 2: 1
OPTION B - NO BEVEL EDG E
NOTES: UNLESS OTHERWI SE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIO NS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FI LENAME: M08AREV13
Figure 32. 8-Lead Small Outline Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor ’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/ .
? 2008 Fairchild Semiconductor Corporation
FAN73932 ? Rev. 1.0.1
www.fairchildsemi.com
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